Programmable logic devices (PLD) such as field programmable gate arrays (FPGA) and complex programmable logic devices (CPLD), are integrated circuits that can be programmed by users to perform customized logic functions. In a typical design process a user defines customized logic functions using a computer aided design software tool, such as schematic capture or hardware description language (HDL). The software tool then implements the design for a specified programmable logic device type using configurable logic block resources available on that device. The implemented design is stored in a configuration data file. This data file is then loaded into a programmable logic device, configuring the programmable logic device to perform the user's defined customized logic functions.
A programmable logic device is typically mounted on a printed circuit board (PCB) as part of an electronic system. At least one voltage regulator device mounted on the printed circuit board, or external to the printed circuit board, provides power supply to the programmable logic device. The electric circuit comprising the voltage regulator, the interconnects from the voltage regulator to the on-die circuits of the programmable logic device, and any decoupling capacitors is called power distribution network (PDN).
Typical programmable logic device dies are fabricated in complementary metal-oxide-semiconductor (CMOS) process. In digital circuits fabricated in CMOS process when a signal transitions from a logic state “false” to a logic state “true” a transient electric current flows from the positive node of the power supply into the digital circuit. Similarly when a signal transitions from a logic state “true” to a logic state “false” a transient electric current flows from the digital circuit into the negative node of the power supply. These transient currents flow through the power distribution network and generate transient voltage drops on the electrical impedance of the power distribution components through which these transient currents flow. As a direct consequence of the transient voltage drops, the on-die positive voltage supply drops momentarily and the on-die negative voltage supply rises momentarily. The on-die circuits see these momentary supply voltage drops and rises as power supply noise. This noise is called switching noise because the switching of signal logic states in the digital circuit generates it.
In a typical programmable logic device multiple signals may switch at the same moment in time increasing the magnitude of switching noise on the positive and negative supplies. This effect is commonly referred to as simultaneous switching noise (SSN). Simultaneous switching noise (SSN) degrade the performance of the programmable logic device circuits. The magnitude of the simultaneous switching noise (SSN) depends on the number of switching gates of the programmable logic device, the switching speed, and the electrical impedance of the power distribution network (PDN).
In general, the power distribution network impedance is a complex quantity having the magnitude and phase dependent on frequency. As a direct consequence, the magnitude and phase of simultaneous switching noise depends on the frequency of operation of the programmable logic device. Most power distribution networks present impedance magnitude peaks at some frequencies, called resonance peaks. If operating frequency of the programmable logic device, or harmonics of the operating frequency, overlap with a resonance peak of the power distribution network, then significant noise is generated on the on-die voltage supplies.
Knowing the frequency characteristics of the power distribution impedance can help reduce the simultaneously switching noise by configuring the programmable logic device to operate at frequencies that do not overlap with the resonance peak frequencies. Alternately, designers can modify the power distribution network circuit so that the resonance peaks do not overlap with operating frequencies or their harmonics, which is typically done through adjusting the values of decoupling capacitors.
Programmable Logic Devices have multiple voltage value power supply domains connected to different functional blocks, like for example the core logic may be connected to one power supply domain while input/output blocks may be connected to a different power supply domain. More, the input/output blocks may be organized in banks, each bank being connected to a different power supply domain. For example an FPGA with eight I/O banks may have nine power supply domains, one for the core logic and a separate one for each I/O bank. Each power supply domain has a separate power delivery network path for electric current; however, due to various coupling mechanisms like for example electromagnetic coupling and coupling through shared ground impedance, there is interaction between different power supply domains. Power supply noise generated in one power supply domain may couple into a second power supply domain degrading the performance of the circuits powered from the second power supply domain. The supply noise and supply noise coupling can be evaluated through modeling and simulation. The most common type of power distribution model is the s-parameter model. Alternately z-parameter, y-parameter, h-parameter, and other similar type of models are used. These models can be created from the physical layout design files of die, package, and PCB. While this approach works well for custom integrated circuit designs where design engineers have access to all the design files of the die, package, and PCB, in programmable logic device (PLD) applications design engineers typically have access only to the PCB layout design files but not to the PLD die and package layout design files. PLD manufacturers do not provide the physical implementation layout files of their products to customers. The present invention overcomes this issue by providing a method to extract the s-parameter model of the power distribution network of a PLD system including the die, package, and PCB structures.
The present invention provides an embedded Vector Network Analyzer (VNA) instrument for power distribution measurements in programmable logic devices that is able to measure on-die the electrical impedance of each power supply domain of a the power distribution network of a programmable logic device (PLD) and the coupling between different power supply domains by using only general configurable logic blocks available in any programmable logic device (PLD), without the need of built-in dedicated circuits.